This simulator can be used as a concrete example so that its multicore parallelization methodology may be readily applied to other simulators. As a stand-alone PowerPC simulation package, it also has many improvements over the original SimpleScalar PowerPC simulator from UT Austin. Hover your mouse over the various items for more details.

• multicore
• power modeling with Wattch
• temperature modeling with HotSpot
• endian fixes
• warnings addressed
• 64-bit counters
• Intel compiler compatibility
• tt6e trace generation
• bzip2 compression
• fsqrt instruction

This software and all accompanying files are distributed "as is". It is not a time-tested infrastructure worked on for years by dozens of graduate students such as M5 or GEMS. What this is, is a rapidly developed project by one graduate student. There are a few conceivable reasons why this infrastructure may be of use to you: full-system simulators may be too bloated, your research could be tied to the PowerPC ISA, or you might already be familiar with and have written code for other versions of the SimpleScalar tool set.

If you do decide to use this infrastructure as a basis for your research, please include citations to the first or both of the following papers in your references:

• James Donald and Margaret Martonosi, "An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation," in Computer Architecture Letters, vol. 5, August 2006.
• Karthikeyan Sankaralingam, Ramadass Nagarajan, Stephen W. Keckler, and Doug Burger, "SimpleScalar Simulation of the PowerPC Instruction Set Architecture," in UT Austin Technical Report: CS-TR-00-04, 2001.

To download the simulator source (latest version: May 9, 2007), please fill out your name and email address. After you have downloaded and gunzipped+untarred the archive, find README.multicore for an overview and brief instructions.

First name:

Last name:

Email address (optional):

Is this for noncommercial use only?

Benchmarks

• For precompiled SPEC CPU2000 binaries (latest set: August 6, 2006) linked statically for AIX 4.3.3, click here.
• For precompiled SPEC CPU2000 binaries (latest set: May 7, 2007) cross-compiled statically for PowerPC Linux (unsupported), click here.
• For precompiled SPEC CPU2000 binaries (latest set: December 13, 2006) cross-compiled statically for PPC64 Linux (even more challenging), click here.
• For (some) precompiled SPEC CPU95 and CPU2000 binaries (source: MIRV) cross-compiled statically for PPC64 Linux (untested), click here.
• For precompiled SPEC CPU2000 binaries (latest set: May 7, 2007) cross-compiled statically for ARM (untested), click here.
• For precompiled SPEC CPU2000 binaries (source: Chris Weaver) cross-compiled statically for Alpha Tru64 UNIX (untested), click here.
• For precompiled SPEC CPU2000 binaries (source: Brad Calder) cross-compiled statically for x86 Linux (untested), click here.

Distribution under an open-source license has the added benefit of allowing outside users to contribute. Any assistance would be appreciated in development of the following features:

• system calls **
• parallel applications **
• PPC Linux ELF *
• Fortran 90 benchmarks *
• power model calibration **
• bus model
• clean memory footprint
• simultaneous multithreading *
• out-of-order pipeline model *
• WinThreads implementation
• multiprogram memory offsetting
• AltiVec instructions
• cross-target support
• specialty simulators

* If you are interested in developing any of these items, I have source code from other simulators such as SimpleScalar Alpha that could be helpful.
** At one time I was working on these particular capabilities, but I eventually gave up. I can provide my unfinished works in progress upon request.

You may contact me at the address shown below.

Last updated May 9, 2007 by

back to home